1. Field of the Invention
The present invention relates to a method of creating an optimized tile-switch mapping architecture in an on-chip bus of a system-on-chip (SoC), and more particularly, to a method of creating an optimized mapping architecture between tiles and switches in a mesh-based on-chip bus, which reduces the energy and the communication delay time required for the communication between cores of an SoC, and a recording medium for recording the method.
2. Description of the Related Art
Conventional chip sets, where separate chips each execute their own functions, are evolving toward SoC technology, where various functional blocks are integrated on a single chip. The SoC integrates a variety of functional blocks called cores on a single chip, including a microprocessor, an on-chip memory, an audio and video controller, a CODEC and a digital signal processor, so as to reduce the size of a product and to decrease the development time and cost.
The cores constituting the SoC can be separately developed, if required. Otherwise, cores that have been developed by specialized developers can be used. This reusability of cores can reduce the time and cost required for developing them.
Sometimes, cores of an SoC require a high data bandwidth, which increases the burden on the transmission and reception of data among the cores. For example, in the case of an SoC including a large-capacity on-chip memory and a controller for processing audio and video signals or a CODEC, considerable time and cost are required for designing the architecture of the data transmission and reception between the functional block cores in the chip.
Generally, buses are used for transferring data between a large number of chips. In an embedded system using an ARM (Acorn RISC Machine) CPU, for example, components such as the CPU, a memory controller and a display controller are interconnected using a bus architecture such as AMBA (Advanced Microprocessor Bus Architecture).
The SoC has been evolving toward the integration of cores on a single chip, and the interconnection of the cores has been developing toward using the bus architecture. Thus, a conventional low-integration SoC employs a chip-level bus architecture without modification. However, as the integration of the SoC is increased, the wires of the bus become narrower, and the characteristics of the wires, such as inductance, resistance and capacitance become significant compared to the sizes of gates constituting the cores. Accordingly, it is difficult to obtain the desired system performance when the conventional bus architecture is applied to the SoC.
Therefore, a network-on-chip (NoC) has been developed, which is a technical field including efficient on-chip bus architecture and design methodology for the SoC, and on-chip buses in a variety of architectures have been recently proposed.
FIG. 1 illustrates a conventional on-chip bus architecture. This on-chip bus architecture 100 was obtained by modifying a part of the bus architecture disclosed in U.S. Pat. No. 5,974,487, assigned to Advanced Micro Devices, Inc. The on-chip bus architecture 100 can be used for an SoC including nine cores.
Referring to FIG. 1, the on-chip bus architecture 100 includes nine cores 110a through 110i, which are the various functional blocks, switches 120a through 120l, which are used for communication between the cores 110a through 110i, and links 130a through 130l and 131a through 131h, which are used for interconnecting the switches 120a through 120l. The links 130a through 130l and 131a through 131h and the switches 120a through 120l are configured in a ring topology, the rings of which form a two-dimensional mesh of the bus architecture. The switches 120a through 120l are positioned at the intersections of the mesh of rings. Each switch receives data from one switch through a link, and transfers it to another switch through another link. Furthermore, each switch transfers data through a link to a core, and transfers data from the core to other cores via other switches.
Here, a link can connect switches bi-directionally or uni-directionally. A bi-directional link can be constructed of a pair of uni-directional wires that transfer data in opposite directions. Otherwise, the bi-directional link can be comprised of a single wire.
When a first core 110a has data that must be transmitted to a second core 110e, the first core 110a transmits the data to a first switch 120a. The first switch 120a transfers the data received from the first core 110a through a first link 131a to a second switch 120d. Finally, the second switch 120d transfers the data received through the first link 131a to the second core 110e. That is, in the on-chip bus architecture 100 of FIG. 1, data transmission and reception between cores is carried out through links connecting switches connected to the cores.
FIG. 2 illustrates mapping among cores, tiles and switches. FIG. 2 includes a core-communication graph and an NoC architecture. The core-communication graph determines cores 210 which will be interconnected in order to construct the on-chip bus architecture 100 of FIG. 1. In FIG. 2, a first core s is connected to second and third cores d and d′.
The NoC architecture includes a plurality of switches 230, a plurality of tiles 220, and a plurality of links connecting the plurality of switches 230, and determines the connection of the tiles 220 and the switches 230. The tiles 220 are spaces where the cores are mounted, and are connected to the switches 230.
In FIG. 2, the first core s is mapped to a first tile k, the second core d is mapped to a second tile l, and the third core d′ is mapped to a third tile l′. One of switches abutting the first tile k is a first switch i, and one of the switches abutting the second tile l is a second switch j. FIG. 2 shows first and second data communication routes x and y from the first switch i to the second switch j.
In the construction of the on-chip bus architecture 100 of FIG. 1, it is important which switches are connected to which tiles if the mapping relationship between the cores and the tiles is already determined. Energy consumption and communication delay time for the transmission and reception of data between connected cores in the mesh-based on-chip bus architecture are proportional to the hop distance between the connected cores. Accordingly, a tile-switch mapping method capable of minimizing the hop distance required for the transmission and reception of data is desired. However, conventional tile-switch mapping methods consider only one-to-one mapping between tiles and switches.
Furthermore, the conventional mapping methods do not propose an optimized mapping architecture for reducing energy consumption and communication delay time required for the transmission and reception of data between cores. Accordingly, a tile-switch mapping method is desired that determines the mapping relationship between cores and switches to minimize the hop distance desired for the transmission and reception of data between cores to thereby minimize energy consumption and communication delay time.